The cost of a PCB design is set by the board itself, not by the clock. A two-layer board and a ten-layer DDR5 board are different products with very different amounts of engineering in them, so a meaningful price has to describe the scope of the work, not a rate per hour.
Most people reach a design quote after a fabrication quote has already landed in their inbox, and the two numbers have little in common. The fab quote prices a physical object made to your drawing. The design quote prices the engineering that decided what that object is and whether it can be built.
In the keyword data behind this post, “pcb design services” carries a click cost of $14.07 against $5.36 for “pcb design”.
What you are actually paying for
A board quote is not one thing. The published breakdown of how such a quote is assembled separates it into three: engineering costs (schematic design, PCB layout, simulation and analysis, component selection, design reviews and documentation), fabrication costs (board materials, layer count, board size, line width and spacing), special processes such as impedance control, testing and shipping, assembly costs (component cost, placement and assembly, test and inspection, tool costs), and EDA software licences and library costs. That decomposition, from Breaking Down PCB Pricing, is the map for what follows.
The engineering line is not a drafting charge. It covers the reasoning that turns requirements into a schematic, the layout decisions that make that schematic work on real copper, the analysis that catches what testing would otherwise catch late, and the documentation that lets the next person pick it up.
The fabrication line is a different economy. Manufacturing is dominated by the etching, drilling, metallising, solder mask, silkscreen and surface finish steps that turn a printed circuit board into a physical object, each scaling with layer count, board area and feature density. The published figures from How Much Does a Printed Circuit Board Cost? are the ones to note: moving from 2 layers to 4 adds roughly 30 to 40 per cent, bulk orders cut the unit cost of multi-layer boards by around 20 to 50 per cent against low-volume orders, and rush orders can raise the price by as much as 25 to 100 per cent. Those are manufacturing economics, not a quote from a design house.
A board quote you already hold tells you very little about the design price, because the fab house prices what it is told to make. If the layer count and impedance targets were set by the design engineer, they were set before a single board was ordered.
We scope the engineering side separately from the manufacturing, which is why our services overview and a fabricator’s quote rarely resemble one another.
A design quote that does not say which of the three ledgers it covers is not a quote. It is a number with an adjective attached.
The cost of a board is set long before anyone talks about price. Layer count, package density and interface speed decide the design hours, and the fabrication quote is a consequence of those decisions.
What drives the design effort
Two engineers quoting the same board differ because their assumptions about the stack-up, the interface and the constraint set differ. The table is the order we work through internally, and the last column is deliberately qualitative: any percentage split would be a rate card we do not publish.
| What changes | Why it moves the design effort | Rough effect on the design budget |
|---|---|---|
| Number of layers | Each layer needs a stack-up decision, a reference plane plan and its own length matching. | Dominant for multi-layer work, minor for a simple two-layer board |
| Board size and component density | Density sets the routing space per net, so power, signal and analog paths compete for room. | Significant, and it compounds with layer count |
| BGA and fine-pitch package count | Escape routing, via arrays, fanout and stencil limits have to be designed, not just routed. | Dominant when present, negligible when absent |
| Interface count and speed | Every differential pair, high-speed link or RF path needs length matching, plane continuity and a stack-up that holds impedance. | Significant to dominant, depending on how many and how fast |
| Number of distinct nets | Net count drives schematic review, connectivity checking, net classing and documentation. | Moderate to significant |
| Power tree and thermal design | Rails at different currents need different copper, return paths and often a different regulator layout. | Significant, and often underestimated |
| Fabricator’s process constraints | Minimum annular ring, spacing, drill-to-drill and mask dam rules set the limits the layout obeys. | Moderate, but decisive when a constraint is missed late |
| Assembly complexity | Polarity and side, dense BGA packages, small passives and connector types affect the assembly drawing and test plan. | Moderate |
| Documentation and DFM scope | Assembly drawings, BOM, pick-and-place output, drill files and a DFM review all have to be produced and checked. | Significant when scoped, negligible when assumed |
| Revision count | Each revision costs time, and one that changes the schematic invalidates layout work already done. | Moderate to significant, depends on how revisions are used |
Read that column as an ordering, not a scorecard. If your board has a BGA and a DDR interface, the BGA and the interface are the work, and the net count is bookkeeping on top. If it is a two-layer control board with no exotic packages, most rows are minor and the quote should be modest.
Interface speed is where boards quietly get expensive. Getting a DDR4 or DDR5 interface right is a different exercise from laying out a UART: byte lanes, fly-by against stub topologies, via transitions inside a pair, and the reference plane arrangement beneath it. The same applies to PCIe, USB, Ethernet and RF. If your board has any of these, the layout is a constraint-solving task rather than a drawing task, and it is worth reading how we scope that work in our high-speed PCB design service.
Getting an accurate quote
Quote accuracy is mostly a function of what you send. Asked to price “a 4-layer board with a USB-C port”, a designer is guessing. Send the following and you get a number you can compare with another supplier’s.
- The schematic, or at minimum a netlist, plus any partial work already done.
- The intended fabricator, if there is one, and their capability document or stack-up.
- Target layer count and the board outline.
- Every interface you need, with data rates or speeds, and the protocol on each.
- Mechanical constraints: connector positions, keepouts and enclosure mounting.
- Power budget or expected current draw per rail, including margin.
- The compliance target, and what evidence you need from the design.
- The deliverables you expect: schematic, layout, fabrication data, BOM, assembly drawings, pick-and-place files, drill files.
- The date you need the first prototype, and the date you need to be in production.
The dates belong on that list too. Schedule pressure changes the work, because a rush review compresses the checks that would normally happen between schematic and layout, and the time available to fix what they find.
Two questions get skipped and both cost money later. The compliance target, because layout decisions that affect an emissions or safety test must be made in the design, not discovered at the lab. And the assembly package, because a layout without pick-and-place data, a BOM and assembly drawings does not get assembled without another round of questions.
Reading a real quote
A real quote itemises. Look for the stack-up and the impedance targets for each interface. Look for a statement that the fabricator’s process constraints are respected, meaning the annular ring, spacing and mask dam rules from a named fabricator rather than from memory. Look for how placement and routing is handled per interface, since a DDR link or an RF section is a design decision and should be described as one. Look for what the DFM review and documentation cover. Look for the revision and support terms.
If a quote is a single number with no breakdown, it is not comparable to anything. It might be cheap because the scope is narrower than you think, and you cannot tell from the number alone. Ask for the breakdown. Our PCB design review service exists for that case: a second opinion on whether the scope and the price match the board. Broader questions are answered on our FAQ page.
Frequently asked questions
How much does a PCB design cost per hour?
We do not publish an hourly rate, and it is a poor proxy anyway. The cost is driven by the board and not by the clock. A designer can move quickly through a dense BGA escape and slowly through an ambiguous power tree, and an hour of each does not carry the same weight. The useful comparison is between two quotes for the same board.
Is it cheaper to have my design done in-house?
Sometimes. In-house makes sense when someone already owns the toolchain, when the board is simple, and when the schedule has room for the learning curve on a new tool or stack-up. It stops making sense for a dense BGA, a multi-layer high-speed design, or a board that has to pass a certification. Layout is a specialist skill and the ramp is real.
What should I send a designer so the quote is accurate?
Send the schematic or netlist, the intended fabricator if there is one, the target layer count and board outline, every interface with its data rate or speed, the mechanical constraints and connector positions, the power budget or current draw, the compliance target, the deliverables you expect, and the date you need the first prototype. That list is the difference between a quotation and an estimate.
How do I tell a cheap quote from a real one?
A real quote itemises the stack-up and impedance targets, shows that the fabricator’s process constraints are respected, describes the placement and routing approach for the interfaces, states what the DFM review and documentation cover, and sets out the revision and support terms. A cheap quote usually does none of these.
How many revisions should a quote include?
Agree the revision count up front, but define the scope of each revision carefully. A revision that adjusts a trace, one that adds a test point, and one that changes the schematic are different amounts of work, and a package of three revisions means nothing until you know which it covers. A schematic change invalidates layout work already done.
What to do next
Send us the schematic or netlist, the fabricator you have in mind, the layer count and outline, the interfaces with their speeds, the mechanical constraints, the power budget, the compliance target, the deliverables and the prototype date. If some of that is undecided, say so, because an undefined requirement is the most expensive thing you can hand a designer.
Request a quote at pcbrouting.com/get-a-quote/. You will get back what the board takes and an honest read on whether we are the right studio for it. If you would rather see the work first, the project portfolio shows finished boards across the categories we take on, which is the fastest way to judge whether our level of detail matches yours.
